The present invention relates to semiconductor memory devices, and more particularly, to data output circuits for controlling the output of data signals in semiconductor memory devices.
A synchronous dynamic random access memory (SDRAM) is required to have high speed, low power consumption, and a multiple bit output, high speed interface. Accordingly, a packet type SDRAM, which can consecutively provide RAS and CAS data, has been proposed. A double data rate (DDR) type SDRAM, which outputs a data signal in synchronism with external clock signals CLK, /CLK and increases the output rate superficially by two times has also been proposed.
A DRAM employing a higher speed interface has also been proposed. High speed interface technology, such as a packet or DDR type interface, requires a modified DRAM controller. Providing external commands is difficult in a packet DRAM, and receiving data signals in accordance with the rising of the external clock signals CLK, /CLK is difficult in a DDR DRAM.
An improved synchronous DRAM (SDRAM) receives external command and addresses together and outputs a data signal in synchronism with the external clock signal of a DRAM controller. The improved synchronous DRAM generates internal signals by dividing the external clock signal in half and further generates a first internal clock signal having a phase of 0.degree. and a second internal clock signal having a phase of 180.degree.. In other words, if the clock frequency of the external clock signal is 400 megahertz, the clock frequency of the first and second internal clock signals is 200 megahertz and the phases of the first and second internal clock signals are offset from each other by half a cycle. In the improved SDRAM, the first and second internal clock signals are generated from the external clock signal. Thus, contrary to when generating the external clock signals CLK, /CLK, the DRAM controller need not be modified. Furthermore, input pins for additional external clock signals are not necessary.
The improved SDRAM acquires a command and addresses, which are output in synchronism with the rising of the 400 megahertz external clock signal, in accordance with the rising of the first and second internal clock signals. When using an output buffer that receives the first and second internal clock signals alternately and outputs a data signal, the data signal is output in synchronism with the rising of the external clock signal. This causes a circuit delay from when the command is acquired to when the data output circuit is activated. Generally, if the circuit delay takes a single cycle or more of an external clock signal, the activation of the data output circuit by the first and second internal clock signals is further delayed. To compensate for such circuit delay, first and second input internal clock signals and first and second output internal clock signals are generated, and the phases of the first and second output internal clock signals are advanced.
However, such an improved SDRAM still has the shortcomings described below.
(1) It cannot be determined whether the command and the addresses were acquired in accordance with the first input internal clock signal (synchronized at 0.degree.) or the second input internal clock signal (synchronized at 180.degree.). Accordingly, it cannot be determined whether the data signal should be output in accordance with the first output internal clock signal or the second output internal clock signal. As a result, if a command is acquired in accordance with the first input internal clock signal or the second input internal clock signal, the output order of the data may be incorrect. Thus, it must be determined whether commands are acquired in accordance with the first input internal clock signal or the second input internal clock signal so that the data signal is always output at a predetermined timing.
(2) Data having a burst length of 1 causes problems during a read operation. The cycle of an internal clock signal used during processing by the synchronous DRAM is longer than the cycle of a divided external clock signal, which is obtained by dividing the external clock signal by one half. That is, a single cycle of the internal clock signal corresponds to two cycles of the external clock signal. However, the read operation of a data having a burst length of 1 requires a signal having the same frequency as the external clock signal.
(3) The output timing of the read data signal is determined by the first and second output internal clock signals and not the first and second input internal clock signals. This results in a delay in the output of the read data signal. The clock count of the first and second output internal clock signals starts when the command is acquired in accordance with the first and second input clock signals. When the clock count reaches a predetermined value, the read data signal is output. Therefore, for example, if a command is acquired in accordance with the first input internal clock signal and the first output internal clock signal corresponding to that first input internal clock signal has already been output, the output timing is determined by the following or next output internal clock signal. In this case, the read data signal is not output within the predetermined number of cycles. This causes a delay in the output of the read data signal.